1. Field of the Invention
The present invention relates generally to an integrated circuit operable in a selected one of a first ("deep power down") mode in which it consumes extremely low power and a second ("active") mode in which it consumes relatively high power. In the deep power down mode of preferred embodiments including CMOS circuitry, a first voltage is supplied to the body of one or more MOS transistors all having a common polarity (N-channel or P-channel), a second voltage is supplied to the source of each MOS transistor, and the voltage difference between the first voltage and the second voltage is selected to achieve a desired decrease in leakage current in each transistor during the deep power down mode.
2. Description of Related Art
For convenience, the following notation is used in the description of the drawings (FIGS. 1-8). The symbol -N (where "N" is any signal name) is used in the specification to denote a signal identified by the corresponding symbol N in the drawings.
The description of FIGS. 1-8 assumes that each signal -N represents a logical "1" when its value (e.g., voltage level) is low (below a threshold), and represents a logical "0" when its value is high (above the threshold). Of course, it is within the scope of the invention to employ circuitry implementing the logical functions described with signals having the opposite polarities.
Throughout the specification, including in the claims, the term "connected" is used (in the context of an electronic component being "connected" to another electronic component) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Many conventional integrated circuits (such as memory circuits) operate in one of: a "deep power down" mode in which all but essential component circuits are shut off to save power (typically, a chip draws no more than a few microamps in a deep power down mode); a "standby" mode in which a somewhat higher current consumption (e.g., as much as 100-500 microamps) can be tolerated; and an "active" (or "enabled") mode in which all component circuits are enabled to perform their intended functions (the chip typically draws tens or hundreds of milliamps of current in the active mode). In this specification, including in the claims, the term "active" mode is used in a broad sense to refer either to the second or third (but not the first) of these three modes. Typically, such circuits have a pad to which an external device asserts a "deep power down" command signal. Such a command signal is a digital signal whose level indicates either that the integrated circuit should operate in a deep power down mode, or that the integrated circuit should operate in an active mode.
For example, FIG. 1 is a simplified block diagram of a conventional CMOS memory circuit (an integrated circuit) which includes the following components: supply voltage circuit 10, address buffers A0 through Ap, address decoder circuits 12 and 14, memory array 16, sense amplifier 18, and output buffer 20. Each of the storage locations of memory array circuit 16 is indexed by a row index (an "X" index output from decoder circuit 12) and a column index (a "Y" index output from decoder circuit 14).
Each of address buffers A0 through Ap is connected to a different address bit pad, and each receives (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
Supply voltage circuit 10 provides an internal voltage (V.sub.CC) to various ones of the components of the FIG. 1 chip (including each of the address buffers) in response to an external voltage (External V.sub.CC) received at pad 9 and a control signal (-DPDown). An external control signal "External -DPDown" is received from an external device at buffer circuit 11. Buffer circuit 11 buffers this signal to generate control signal -DPDown and asserts control signal -DPDown to circuit 10.
Supply voltage circuit 10 is a CMOS inverter comprising P-channel MOS transistor P1 (which is a large P-channel device that can support the current requirement of the entire FIG. 1 chip) and N-channel MOS transistor N1. The source of P1 receives externally supplied voltage "External V.sub.CC ", the drain of P1 is connected to the drain of N1, and the source of N1 is connected to ground. The gate of each of transistors P1 and N1 is connected to the output of buffer circuit 11 so as to receive control signal -DPDown.
When control signal -DPDown is high, the internal voltage (V.sub.CC) output from circuit 10 to various components of the FIG. 1 chip has a relatively high value (for example, 5 or 5.5 volts). This internal voltage enables each of the components to which it is supplied to operate in an active mode (in which it consumes relatively high power) unless such component is wholly or partially disabled by some other external control signal (not shown). When the components of the FIG. 1 chip are all enabled, the FIG. 1 chip operates in an active mode (for example to execute a read or write operation).
In contrast, when -DPDown is low, the FIG. 1 chip operates in an inactive mode (known as the "deep power down" mode). In the deep power down mode, the internal voltage (V.sub.CC) line is grounded (i.e., the internal voltage output from circuit 10 to components of the FIG. 1 chip has a relatively low value). In response to this (grounded) internal voltage, each of the components enters an inactive mode ("deep power down" mode) in which it consumes relatively low power.
In the active mode (in response to a high value of -DPDown), the FIG. 1 chip can execute a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to X address decoder circuit 12 and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to Y address decoder circuit 14. In response to these address bits, X address decoder 12 asserts a row address to memory array 16 and Y address decoder 14 assert a column address to memory array 16. In response to a write command supplied from control circuitry (not shown in FIG. 1), a quantity of data is written to the storage location of array 16 determined by the row and column address.
Also in its active mode, the FIG. 1 chip responds as follows to a "read" command. Each of the address buffers A0 through An asserts one of the input address bits X0-Xn to X address decoder circuit 12 and each of address buffers An+1 through Ap asserts one of the input address bits Y0-Ym to Y address decoder circuit 14. In response to these address bits, the X and Y address decoders assert a row address and a column address to memory array 16, array 16 outputs to sense amplifier 18 a data signal indicative of a data value stored in the storage location determined by the row and column address, amplifier 18 asserts a corresponding amplified data signal to output buffer 20, and output buffer 20 asserts a corresponding "Output Data" signal at an external pin of the FIG. 1 circuit.
FIG. 2 is an inverter circuit Ix of a type included in a typical implementation of each of address buffers A0 through Ap of FIG. 1. The inverter of FIG. 2 circuit receives a TTL level input voltage Vin (indicative of an address bit), and outputs an inverted (and level-translated) voltage Vout in response.
FIG. 3 is a typical implementation of inverter circuit Ix of FIG. 2. The circuit of FIG. 3 is a CMOS inverter comprising P-channel MOS transistor P2 and N-channel MOS transistor N2. The source of P2 is connected to internal supply voltage V.sub.CC (supplied from supply voltage circuit 10), the drain of P2 is connected to the drain of N2, and the source of N2 is connected to ground. The gate of each of transistors P2 and N2 receives input voltage Vin. When voltage V.sub.CC is high (e.g., 5 or 5.5 volts), the FIG. 3 circuit responds to V.sub.in as follows. When V.sub.in is low, transistor P2 is "on" and transistor N2 is "off," so that the voltage level (V.sub.out) of FIG. 3 is pulled "high" by V.sub.CC. When V.sub.in is high, transistor P2 is "off" and transistor N2 is "on," so that the output node is pulled "low."
FIG. 4 is a typical CMOS implementation of the inverter circuit of FIG. 3. The source and drain of P-channel transistor P2 are formed in well 30 (composed of N-type semiconducting material). Well 30 is formed in substrate 40 (composed of P-type semiconducting material), as are the source and drain of N-channel transistor N2. The large capacitance on the source of P2 is represented by capacitor C1 (shown connected between the source of P2 and ground). In typical implementations of the FIG. 1 memory chip, it is desirable that lengths, L and L' respectively, of the channels of transistors P2 and N2 are very short for maximum speed of operation.
The chip will draw a total of on the order of tens of milliamps to hundreds of milliamps when in the active mode. It is often desired (e.g., for laptop computer applications of FIG. 1 in which memory array 16 is an array of flash memory cells with four megabit density) that FIG. 1 consume no more than a few microamps of current in a deep power down mode (when the control signal -DPDown is low).
However, there is a significant problem inherent in operation of the conventional circuit described with reference to FIGS. 1-4 in transitions from the deep power down mode to the active mode.
The problem is that, as a result of supply voltage circuit 10's decoupling of External V.sub.CC from the address buffers (and other components), a long time is required to come out of the "deep power down" mode in response to a low-to-high transition of signal -DPDown. One mechanism that contributes to this problem is that the memory elements of array 16 must be able to be read upon transition to the "active" mode. This requires preconditioning of all relevant voltage levels to their proper values. Since all these voltages have been brought down to zero as a result of V.sub.CC shutting off, restoring these values requires a significant amount of time.
Another mechanism contributing to the problem is that if the voltage applied to the well of a P-channel transistor (during a "deep power down" to "active" transition) is increased too rapidly, the undesirable effect of latch-up might occur. For example, in typical implementations of FIG. 1, many P-channel transistors share a common well (e.g., well 30 of FIG. 4) formed in a substrate of N-type semiconductor material (e.g., substrate 40 of FIG. 4). To power up each such transistor during a "deep power down" to "active" mode transition, the voltage V.sub.CC applied to the well is increased from ground to the appropriate value (e.g., 5.5 volts). However, if the voltage applied to the well increases too rapidly, the resulting charge injection from the substrate to the well can cause latch-up. Thus, the voltage applied to the well must be increased sufficiently slowly to control undesirable charge injection from the substrate (e.g., substrate 40 of FIG. 4) and thereby avoid latch-up. These mechanisms make it difficult (or impossible) to meet the typical specification of a transition time of on the order of 100 nanoseconds for a "deep power down" to "active" mode transition.
Another problem, inherent in conventional memory chips which apply External V.sub.CC to their component transistors in all operating modes, is unacceptably high subthreshold leakage current (e.g., leakage between the source and drain of transistor P2 of FIG. 4) and thus unacceptably high power consumption in the transistors to which the External V.sub.CC voltage remains coupled during a deep power down mode. Such leakage occurs (unless reduced in accordance with the present invention) due to inherent defects in the transistor manufacturing process, and is especially significant with transistors having very short channel lengths (e.g., implementations of transistors P2 and N2 of FIG. 4 having very short channel lengths L and L'). For example, typical implementations of transistor P2 of FIG. 4 have leakage current in the range from 1 nA to 5 nA in the deep power down mode. Thus, in embodiments of a conventional memory chip which include twenty address buffers (each address buffer including one such FIG. 4 inverter), and an implementation of decoder circuit 12 including 4000 of the FIG. 4 inverters, the address buffers and circuit 12 will themselves draw a total of 4-20 microamps in the deep power down mode. This current is much greater than the typical design specification of 1 microamp for current consumption of a memory chip in the deep power down mode.
The leakage problem described in the previous paragraph could be reduced by employing transistors having longer channel lengths. However, this would undesirably decrease performance by decreasing the current drive capability of the transistors. In order to remedy this situation, it would be necessary to increase the width of the transistors and thus the required size (footprint) of a VLSI implementation.